For systems that must sense, interpret, decide, and act under tight constraints
Meroplane's Loom is a purpose-built inference engine for the real edge problem: dense neural math, long-lived state, sparse and routed execution, signal transforms, fast memory movement, and bounded local control under one architecture. Loom keeps the mission loop local, end to end.
Loom is projected to span roughly a 4 to 39 watt SoC power envelope, from compact sensor processors to larger edge inference engines, while keeping the software model and ISA consistent across the family.
Local control flow, event synchronization, bounded execution
Loom excels in the case when the model is the controller. When the AI is the loop, the inference path becomes hard real-time control and has to be treated like avionics.
Sensor ingress through a deterministic DMA engine, into local SRAM, through inference, out to the actuator, with the host only loading the model and watching health. The control path never leaves the chip.
Loom is built for more than LLMs. It pairs dense neural compute with FFT/FWHT-class transforms, state-space-friendly execution, sparse routing, and real data-movement primitives so radio, audio, video, and language workloads can live on one platform.
Drones, radios, cameras, vehicles, industrial sensors, and other thermally constrained systems need local compute designed for consequence, in envelopes where a GPU simply cannot operate.
Loom is a family of parts spanning a roughly 4 to 39 watt range, from compact sensor-class configurations to high-density edge-LLM parts. Every part runs the same software, the same models, the same binary format. Array size and tile count are microarchitectural; software sees the same ISA everywhere. A model compiled for the smallest part runs unmodified on the largest. It just runs faster.
| Class | Relative compute | SoC power | Target |
|---|---|---|---|
| Compact | Entry | ~4-10 watts | Sensors, cameras, instruments, medical |
| Standard | Mid | ~12-17 watts | Robotics, security, network appliances |
| High-density | Top | ~30-39 watts | Edge LLM, defense, cognitive radio |
Configurations and counts are still being finalized. External memory is commodity DRAM. Power and area numbers are pre-silicon projections; the design is being characterized now.
Three specialized units, zero wasted silicon
A scalable systolic array, sized per part, handles dense matrix multiplication, the bulk of transformer and MLP inference cost. Native support for FP32, BF16, FP8, INT8, INT4, INT3 packed, INT2, 1.58-bit ternary, and binary keeps Loom efficient from full-precision bring-up to extreme low-bit deployment.
Loom eliminates wasted data movement. By fusing bias, scaling, requantization, and activations directly into the MXU pipeline, a full projection executes in a single pass.
The SCE is Loom's vector, spectral, and sequence engine. It handles reductions and normalization, Top-K and argmax sampling, RoPE and mask application, codebook-based dequantization and decoded-view lookup, and native linear recurrence scans for Mamba- and S4-class models. Its dual-mode butterfly datapath runs FFT/IFFT and FWHT in hardware, with causal and overlapped windowing and complex spectral filtering and correlation, so the same engine covers telecom and SDR pipelines, spectral sequence models, and long-context compression on one chip.
Working with the SCE, Loom's Smart DMA handles gathers, scatters, transposes, and paged-attention-style assembly so data can move between on-chip SRAM and external memory without burning MXU cycles or forcing host-side reshaping.
Retrieval runs in hardware with native structured sparsity. The SCE reduces scores, selects Top-K, and compacts survivors on-chip, so a retrieval or sparse-analytics pass narrows millions of candidates to a shortlist and hands only that shortlist to the dense model. The compaction is silicon: the data-movement penalty that makes Graph-RAG impractical at the edge never happens.
The DMA engine moves higher-rank tensors as a hardware primitive: streaming descriptors keep multi-frame tensors, latent video windows, and rolling sensor volumes live as native working sets. Models reason over time directly, without the "flatten-and-reshape" tax a software stack pays to fake a 4D view out of 2D copies.
An on-chip RISC-V control plane handles local loops, conditionals, event waits, and orchestration for the MXU, SCE, and DMA without keeping a host CPU in the critical path. The ACP owns launch policy, threshold checks, stop conditions, retries, mailboxes, and safe fallback behavior, so execution stays local, observable, and bounded.
Local control, bounded execution: The host becomes supervisory, not real-time. That shortens sensor-to-decision latency, simplifies the surrounding system, and makes timeouts, clamping, and fallback behavior explicit parts of the design.
Model- and kernel-level workflows lowered by loomc, executed through libloom, inspected with loomctl, and extensible through Triton, with the ACP running the device.
INT8 normally needs per-model calibration. Loom does not. The compiler rotates and quantizes weights offline with a Hadamard transform that spreads outliers uniformly, and the Sparse Compute Engine applies the matching transform to activations at runtime, letting quantization use its full dynamic range at every bitwidth. No calibration required.
| Format | Bits | Fidelity | 70B Footprint | Notes |
|---|---|---|---|---|
| INT8 | 8 | Perfect | 70 GB | No calibration required |
| INT4 | 4 | Near-lossless | 35 GB | Rotation-assisted integer path |
| INT3 | 3 | High | 26 GB | |
| INT2 | 2 | Moderate | 18 GB | u-law companding |
| Ternary | 1.58 | Moderate | 14 GB | {-1, 0, +1} weights. Multiply-free. Beats INT2 at smaller size |
| Binary | 1 | Usable | 9 GB | Extreme compression for capacity-constrained deployments |
Fidelity labels reflect model-level, rotation-assisted post-training quantization results. They are not measured silicon benchmarks and vary by model and task.
The chip runs the mission
Load weights, define the mission, and keep the loop local. The ACP can own launch policy, stop conditions, threshold checks, mailboxes, and safe fallback behavior without depending on continuous host supervision.
True Edge Autonomy: Inference and control continue through link loss, intermittent connectivity, or host-side interruptions. Essential for defense, vehicles, and remote industrial applications.
Loom can keep the newest window exact while it compresses or compacts the older tail, making the policy observable.
Quantifiable Context Gains: Stretch a 32K context window to 128K via native KV compression, and gain an additional 50-70% memory savings from semantic KV deduplication in document-heavy workloads. Maximizes the local working set before synchronizing to external systems.
Highly optimized for recurrent and state-space models. Fixed-size recurrent state plus block streaming keeps per-step memory flat as the sequence grows.
Always-On Capability: Process hours-long audio, video, telemetry, or navigation streams without context-window blowups. 24/7 monitoring on-device.
For diffusion, Monte Carlo, and branch-heavy planners, Loom can regenerate the same perturbations and restore checkpointed state, so a system can explore multiple paths and replay exactly what happened without storing every sampled tensor it tried.
Loom supports bounded local update loops: adapter refresh, calibration, reward/statistics updates, and small corrective microsteps that happen on the device.
Hardware-visible bounds
For safety-critical systems, the ACP enforces output bounds in hardware. Neural network outputs are clamped before reaching actuators, regardless of what the model produces. Model commands cannot exceed configured actuator limits.
ACP cycle budgets give autonomous loops a strict time bound. If a loop misses its budget, the device faults or falls back by policy. Your control loops meet their deadlines or fail safely.
Memory windows and execution-context boundaries are designed to keep one context from trampling another's control or data ranges. Enforce strict separation for fault containment, mixed criticality, and multi-mission workloads sharing a single device.
Bounded behavior is only useful if it is visible. Event signaling, completion writeback, diagnostics tooling, and lightweight trace markers are built directly into the hardware surface. The host can tell exactly what executed, what was clamped, what timed out, and which fallback path fired.
Radical Transparency: Build systems that don't just output answers, but can precisely explain how and why they executed their tasks.
Versioned buffers, event surfaces, and trace markers let teams snapshot state, replay branches, and see what actually ran. That turns Loom from a black box into something product teams can debug, tune, and ship with confidence.
From frontier LLMs to RF and robotics, on one architecture
Loom's hardest case is the closed control loop, where the model is the controller and the decision and the deadline are the same event. The same host-free, deterministic architecture runs the broader inference surface around that core: large models held local, signal pipelines kept on-chip, and vision and structured-data workloads that benefit from bounded scheduling and predictable latency.
Dense transformers, fine-grained MoE, long-context and reasoning models (Llama 4, Qwen3, DeepSeek-V3, DeepSeek-R1, Kimi K2 Thinking). Batch-1 decode and host-free MoE routing run at silicon speed on a local box.
State space models, linear and spectral attention, recurrent and continuous-time networks (Mamba, SSMs, Linear RNNs). The SCE processes the state updates directly, removing KV-cache bloat.
Neural receivers, beamforming and phased-array control, software-defined radio, and spectrum sensing. Streaming I/Q lands in SRAM and runs through the spectral datapath without a host round-trip.
Vision transformers, detection and segmentation, diffusion and generation, and event-based neuromorphic pipelines (Qwen3-VL, Llama 3.2 Vision, Pixtral). Multi-camera tensors stay resident on-device.
Graph neural networks, tabular and time-series models, embedding search, and associative memory. Large embedding tables stay resident in commodity DRAM with hardware sparse gather.
Learned control policies, physics-informed networks, navigation and SLAM, and genomics. The ACP runs the policy as the hard real-time controller, sensor to actuator on one chip.
